As is well known, a final output stage of a generic electronic circuit basically includes a drive portion intended for powering a load whichever. Thus, the output stage should be capable of draining or taking up current from the load, according to necessity and the type of application involved.
Countless configurations have been proposed in the prior art for the output stage. FIG. 1 attached hereto shows schematically one of the commonest of such output stage configurations.
The stage shown in FIG. 1 comprises a complementary pair of MOS transistors connected in series with each other, between a first voltage reference Vdd and a second voltage reference Vss, wherein the latter may either be a negative supply or a ground.
Complementary pairs of MOS transistors are those more often employed in output stages on account of the definite advantages that they afford in the respect of control logics; however, the considerations made herein below would also apply to output stage configurations incorporating bipolar transistors or any other pairs of MOS transistors.
The first transistor M7 in the complementary pair is a pull-down transistor of either the NMOS or the DMOS type, and has its body terminal connected to the source terminal.
The second transistor M6 in the complementary pair is a pull-up transistor of the thin oxide PMOS type, and has its body terminal connected to the source terminal.
The transistors M6 and M7 are connected to each other through their respective drain terminals, which terminals coincide with an output node OUT. An electric load, not shown, is connected between the output node OUT and ground.
The electric load is driven alternately by the PMOS transistor M6 or the NMOS transistor M7, according to whether the operation phase is one of sourcing or of sinking.
Respective driving stages have their respective outputs connected to the gate terminals of the transistors M6 and M7. Only the driving stage of the PMOS transistor M6 is shown in FIG. 1.
FIG. 2 shows a second example of an output stage incorporating a pair of NMOS and PMOS transistors M15 and M23. These transistors are again connected together at the output node OUT, and a driving stage of greater complexity than in the previous example of FIG. 1 is provided for the PMOS transistor M23.
FIG. 3 shows schematically a further embodiment wherein all the PMOS transistors shown in FIG. 2 are replaced with similar thick oxide PMOS power transistors.